Current demands for high density and performance associated with ultra large scale integration require design rules of about 0.18 microns and under, increased transistor and circuit speeds and improved reliability. As device scaling plunges into the deep sub-micron ranges, it becomes increasingly difficult to maintain performance and reliability.
Devices built on the semiconductor substrate of a wafer must be isolated. Isolation is important in the manufacture of integrated circuits which contain a plethora of devices in a single chip because improper isolation of transistors causes current leakage which, in turn, causes increased power consumption leading to increased noise between devices.
In the manufacture of conventional complementary metal oxide semiconductor (CMOS) devices, isolation regions, called field dielectric regions, e.g., field oxide regions, are formed in a semiconductor substrate of silicon dioxide by local oxidation of silicon (LOCOS) or by shallow trench isolation (STI). A conductive gate, such as polysilicon, is also formed on the substrate, with a gate oxide layer in between.
A polysilicon layer is deposited on gate oxide. Thereafter, a patterned photoresist mask is formed on the polysilicon layer and the polysilicon layer--oxide layer is etched to form conductive gates with a gate oxide layer in between. Dielectric spacers are formed on sidewalls of the gate, and source/drain regions are formed on either side of the gate by implantation of impurities.
Photolithography is conventionally employed to transform complex circuit diagrams into patterns which are defined on the wafer in a succession of exposure and processing steps to form a number of superimposed layers of insulator, conductor and semiconductor materials. Scaling devices to smaller geometries increases the density of bits/chip and also increases circuit speed. The minimum feature size, i.e., the minimum line-width or line-to-line separation that can be printed on the surface, controls the number of circuits that can be placed on the chip and directly impacts circuit speed. Accordingly, the evolution of integrated circuits is closely related to and limited by photolithographic capabilities.
An optical photolithographic tool includes an ultraviolet (UV) light source, a photomask and an optical system. A wafer is covered with a photosensitive layer. The mask is flooded with UV light and the mask pattern is imaged onto the resist by the optical system. Photoresists are organic compounds whose solubility changes when exposed to light of a certain wavelength or x-rays. The exposed regions become either more soluble or less soluble in a developer solvent.
There are, however, significant problems attendant upon the use of conventional methodology to form conductive gates with gate oxide layers in between on in a semiconductor substrate. For example, when a photoresist is formed on a highly textured surface such as polysilicon, and exposed to monochromatic radiation, undesirable standing waves are produced as a result of interference between the reflected wave and the incoming radiation wave. In particular, standing waves are caused when the light waves propagate through a photoresist layer down to the polysilicon layer, where they are reflected back up through the photoresist.
These standing waves cause the light intensity to vary periodically in a direction normal to the photoresist, thereby creating variations in the development rate along the edges of the resist and degrading image resolution. These irregular rejections make it difficult to control critical dimensions (CDs) such as linewidth and spacing of the photoresist and have a corresponding negative impact on the CD control of the conductive gates and gate oxide layers.
There are further disadvantages attendant upon the use of conventional methodologies. For example, distortions in the photoresist are further created during passage of reflected light through the polysilicon layer which is typically used as a hardmask for etching. Specifically, normal fluctuations in the thickness of the polysilicon layer cause a wide range of varying reflectivity characteristics across the polysilicon layer, further adversely affecting the ability to maintain tight CD control of the photoresist pattern and the resulting conductive gates and gate oxide layers.
Highly reflective substrates accentuate the standing wave effects, and thus one approach to addressing the problems associated with the high reflectivity of the silicon nitride layer has been to attempt to suppress such effects through the use of dyes and anti-reflective coatings below the photoresist layer. For example, an anti-reflective coating (ARC), such as a polymer film, has been formed directly on the polysilicon layer. The ARC serves to absorb most of the radiation that penetrates the photoresist thereby reducing the negative effects stemming from the underlying reflective materials during photoresist patterning. Unfortunately, use of an ARC adds significant drawbacks with respect to process complexity. To utilize an organic or inorganic ARC, the process of manufacturing the semiconductor chip must include a process step for depositing the ARC material, and also a step for prebaking the ARC before spinning the photoresist.
There exists a need for a cost effective, simplified processes enabling the formation of an ARC to prevent the negative effects stemming from the underlying reflective materials during photoresist patterning.
The present invention addresses and solves the problems attendant upon conventional multi-step, time-consuming and complicated processes for manufacturing semiconductor devices utilizing an ARC.